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Product Specifications
24 buffered TTL digital I/O lines on a single-wide IndustryPack
64 mA +15/-5 V operation
Each line programmable as input or output
Double-buffered input and output
Cascadable external clock triggers double-buffering
Form Factor Single-wide Type I IndustryPack
IndustryPack Interface Complies with ANSI/VITA-4
Interface Speed 8 MHz
Wait States None
number of Digital Lines 24 individually programmable and input or output
Input Driver +15/-5 V range
Logic threshold of 1.25 V with 50 mV hysteresis
Output Driver Open collector transistor with 1 kOhm pullup
64 mA Ic for Vol=0.80 V
ESD Protection None
Interrupts None
Power Requirements (no load) +5 VDC, 510 mA typ
Environmental Operating temperature: -0 to +70°C
Humidity: 5 to 95% non-condensing
Storage: –40 to +85°C
The IP-UNIDIG-I-E’s is manufactured by SBS Technologies (Abaco Systems & Greenspring), a 24 Differential I/O IndustryPack Module, it’s a part of the IndustryPackTM Family of modular I/O Components. It provides 24 lines of digital I/O, with any line capable of generating an interrupt. All the I/O lines feature greenSpring’s unique lineSafe electrostatic discharge (ESD) protection circuit, making the IP ideally suited for rugged industrial applications. each line may be dynamically and individually configured for either input or Output. A 16-bit word and 8-bit byte operations are supported. The IP-unidig-i-e is pin and software compatible with the IP-UNIDIG-E Industrypack.
The IP-UNIDIG-I-E conforms to the industry Pack interface specification. This guarantees compatibility with multiple support modules. because the iPs may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one support module with final system implementation on a different one.
The Industry standard 50-pin interface cable may be terminated in a screw terminal block, and OPTO22 direct I/o interface module, or user determined hardware. alternate grounds on this cable assure reliable signals. the interrupt latch circuits are edge sensitive with programmable polarity and are controlled through the following five 24-bit registers: interrupt pending, interrupt requests, interrupt polarity, interrupt enable, and interrupt clear. each line corresponds to one bit in each of the registers, making programming uniform and simple. this architecture also prevents the loss of an event during the execution of the interrupt service routine.
writing one to any line turns off the output driver, allowing a passive pull up resistor to set the line to a logic high. writing a zero to any line turns on the driver, driving the line to a logic low. for input use, a one is written to the corresponding line - this is the power up default. for output use, the binary value desired is written to the corresponding line.
two separate locations in i/o space are provided for each signal line. the first location is used to set the output state and also to read back the written value at the internal latch. this read back functions is valuable to suppoert bit operations (which are implemented by processors as read-modify-write cycles.) it is also useful in debugging, making it possible to observe directly the last written value to the port. the second locations is the direct read port, which is always used for reading input values.
Alternative Part No. IP-Unidig-I-E, 91411543, 96064 , IP Unidig, IP-UNIDIG, IPUNIDIG, IP UNIDIG
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